2. >7 years of experience in high-speed (DC-30GHz) analog/mixed-signal IC development using SiGe BiCMOS and/or CMOS, including >3 years of experience in design of clock-and-data-recovery (CDR) products.
3. Design experience with critical high-speed CDR sub-components, such as VCO, phase/frequency detetor, PLLs,input/output equalizers, etc.
4, 熟悉SiGe, CMOS, SOI半导体工艺.
5.Expert user of Cadence Virtuoso, Spectre, and Assura, etc. EDA software for device modeling, simulation, layout, parasitic extraction and design/layout optimization.